HeapCrash / Challenges / Encoder ISR at top priority

Encoder ISR at top priority

An encoder interrupt passes position samples to a FreeRTOS control task through a queue. The interrupt was set to priority 0 'so it is never delayed'. The system runs for hours, then hard-faults inside a kernel list function. The control task, which has the highest task priority, also sometimes reacts up to a full tick late to a sample. configMAX_SYSCALL_INTERRUPT_PRIORITY is 5 (shifted: 0x50).

The code

Embedded C for Cortex-M. It compiles. There are 3 real bugs in it: the kind that pass a bench test and fail in the field.

void encoder_init(void)
{
    NVIC_SetPriority(EXTI9_5_IRQn, 0);
    NVIC_EnableIRQ(EXTI9_5_IRQn);
}

void EXTI9_5_IRQHandler(void)
{
    BaseType_t woken;
    EXTI->PR1 = EXTI_PR1_PIF7;
    int32_t pos = encoder_read();
    xQueueSendFromISR(pos_q, &pos, &woken);
}

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