SPI DMA on a cached core

The code

Embedded C for Cortex-M. It compiles. There are 3 real bugs in it: the kind that pass a bench test and fail in the field.

static uint8_t tx_buf[12];
static uint8_t rx_buf[12];
static uint32_t frames_ok;

void spi_xfer(const uint8_t *cmd, size_t n)
{
    memcpy(tx_buf, cmd, n);
    spi_dma_start(tx_buf, rx_buf, n);
}

void spi_dma_rx_done(void)
{
    SCB_InvalidateDCache_by_Addr(rx_buf, sizeof rx_buf);
    if (rx_buf[0] == 0xA5) frames_ok++;
    handle_reply(rx_buf);
}

What an interviewer expects

• Point to each line you'd stop in a code review.
• Say what actually breaks: the failure mode, not just the rule it violates.
• Fix it, then defend the fix when asked the follow-up.

The bugs, reference fixes and the follow-up question are in the practice app, after you've tried it.

Companies that test this

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