SoC architecture and performance: interview prep

Interview questions

Key points for each answer are in the app's question bank.

1. Why do caches cause problems with DMA, and how do you fix them?Intermediate
2. MPU versus MMU: what's the difference?Intermediate
3. When do you need memory barriers on Cortex-M?Advanced
4. Design communication between two cores on a multicore MCU.Advanced
5. What is scatter-gather DMA?Intermediate
6. How do you measure execution time precisely on a Cortex-M?Intermediate
7. A routine is too slow. How do you approach optimising it?Intermediate
8. What are TCM and why use them?Intermediate
9. How do flash wait states affect performance?Intermediate
10. Why does alignment matter for performance?Intermediate
11. What are SIMD or DSP instructions on Cortex-M4/M7 and when do they help?Advanced
12. What is bus contention on an SoC, and how does it show up?Advanced

Hands-on challenges

Design rounds

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